? semiconductor components industries, llc, 2001 april, 2001 rev. 5 1 publication order number: cs8311/d cs8311 micropower 10 v, 100 ma low dropout linear regulator with reset and enable the cs8311 is a precision 10 v micropower voltage regulator with very low quiescent current (100 m a typ at 100 m a load). the 10 v output is accurate within 4.0% and supplies 100 ma of load current with a typical dropout voltage of only 400 mv. microprocessor control logic includes an enable input and an active reset . the active reset circuit includes hysteresis, and operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits by more than 1.0 v typ. the logic level compatible enable input allows the user to put the regulator into a shutdown mode where it draws only 20 m a typical of quiescent current. the regulator is protected against reverse battery, short circuit, over voltage, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. features ? 10 v 4.0% output ? low 100 m a quiescent current ? active reset ? enable input for on/off and active/sleep mode control ? 100 ma output current capability ? fault protection +60 v peak transient voltage 15 v reverse voltage short circuit thermal overload ? low reverse current (output to input) http://onsemi.com so8 d suffix case 751 1 8 reset gnd 1 8311 alywx 8 nc enable nc v out sense v in v out pin connections and marking diagram a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information cs8311yd8 so8 95 units/rail cs8311ydr8 so8 2500 tape & reel
cs8311 http://onsemi.com 2 enable + bandgap reference + sense current limit gnd reset v out sense v out error amplifier figure 1. block diagram v in current source (circuit bias) over voltage shutdown thermal protection reset comparator absolute maximum ratings* rating value unit v in 38 v peak transient voltage (46 v load dump @ v in = 14 v) 60 v enable , reset 0.3 to +10.4 v esd susceptibility (human body model) 2.0 kv junction temperature range 40 to +150 c storage temperature range 55 to +150 c lead temperature soldering: reflow (smd styles only) (note 1.) 230 peak c 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed.
cs8311 http://onsemi.com 3 electrical characteristics (11 v v in 26 v; i out = 1.0 ma; 40 t a 125, 40 c t j 150 c; unless otherwise specified.) characteristic test conditions min typ max unit output stage output voltage, v out 11 v < v in < 26 v, 100 m a i out 100 ma 9.60 10.00 10.40 v dropout voltage (v in v out ) i out = 100 ma i out = 100 m a 400 100 600 150 mv mv load regulation v in = 14 v, 100 m a i out 100 ma 5.0 100 mv line regulation 11 v < v < 26 v, i out = 1.0 ma 5.0 100 mv quiescent current, (i q ) active mode i out = 100 m a i out = 50 ma i out = 100 ma 100 4.0 12 250 6.0 20 m a ma ma quiescent current, (i q ) sleep mode v out = off, v in = 12 v, v enable = 2.0 v 20 50 m a ripple rejection 14 v in 26 v, i out = 100 ma, f = 120 hz 60 75 db current limit 105 200 ma short circuit output current v out = 0 v 25 125 ma overvoltage shutdown v out 1.0 v 30 34 38 v reverse current v out = 5.0 v, v in = 0 v 100 250 m a enable input (enable ) threshold high (v out off) 1.4 2.0 v threshold low (v out on) 0.6 1.4 v input current v enable = 2.4 v 30 100 m a reset function (reset ) reset threshold high (v rh ) v out increasing 8.50 9.00 v out 0.50 v reset threshold low (v rl ) v out decreasing 8.30 8.90 v out 0.45 v reset hysteresis (high low) 50 100 200 mv reset output leakage reset = high v out v rh 25 m a output voltage low (v rlo ) r reset = 10 k, 1.0 v v out v rl 0.1 0.4 v output voltage low (vr peak ) r reset = 10 k, v out , power up, power down 0.6 1.0 v package lead description package lead # so8 lead symbol function 1 v out 10 v, 4.0%, 100 ma output. 2 v out sense kelvin connection which allows remote sensing of output voltage for improved regulation. if remote sensing is not required, connect to v out . 3 enable logic level switches output off when toggled high. 4 gnd ground. all gnd leads must be connected to ground. 5 reset active reset (accurate to v out 1.0 v). 6, 7 nc no connection. 8 v in input voltage.
cs8311 http://onsemi.com 4 circuit description voltage reference and output circuitry output stage protection the output stage is protected against overvoltage, short circuit and thermal runaway conditions (figure 2). figure 2. typical circuit waveforms for output stage protection i out load dump v in v out current limit short circuit > 30 v if the input voltage rises above 30 v (e.g. load dump), the output shuts down. this response protects the internal circuitry and enables the ic to survive unexpected voltage transients. should the junction temperature of the power device exceed 180 c (typ) the load current capability is reduced thereby preventing thermal overload. this thermal management function is an effective means to prevent die overheating since the load current is the principle heat source in the ic. regulator control functions the cs8311 contains two microprocessor compatible control functions: enable and reset (figure 3). figure 3. circuit waveform (1) = no reset delay capacitor v in v out enable reset (2) = with reset delay capacitor vr lo vr peak vr peak for 11 v < v in < 26 v v in(h) v rh on v rl off (1) (2) enable function the enable function switches the output transistor on and off. when the voltage on the enable lead exceeds 1.4 v typ, the output pass transistor turns off, leaving a high impedance facing the load. the ic will remain in sleep mode, drawing only 50 m a (max), until the voltage on this input drops below the enable threshold. reset function a reset signal (low voltage) is generated as the ic powers up until v out is within 1.0 v of the regulated output voltage, or when v out drops out of regulation, and is lower than 1.1 v below the regulated output voltage. a hysteresis of 50 mv is included in the function to minimize oscillations. the reset output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic thereby guaranteeing that the reset signal is valid for v out as low as 1.0 v. figure 4. rc network for reset delay v out cs8311 5.0 v to m p and system power reset r rst to m p reset port c rst c out an external rc network on the lead (figure 4) provides a sufficiently long delay for most microprocessor based applications. rc values can be chosen using the following formula: r tot c rst t delay ln v t v out v rst v out where: r rst = reset delay resistor r in = m p port impedance r tot = r rst in parallel with r in c rst = reset delay capacitor t delay = desired delay time v rst = v sat of reset lead (0.7 v @ turn on) v t = reset threshold.
cs8311 http://onsemi.com 5 application notes v bat switch q1 500 k w 0.1 m f 500 k w 100 k w 100 k w c rst c out r rst v out reset enable v in figure 5. microprocessor control of cs8311 using external switching transistor q1 cs8311 gnd to m p to m p to load i/o 10 v, 100 ma the circuit depicted in figure 5 lets the system control its power source, the cs8311 regulator. a switch (potentially an i/o port on microprocessor) is used to drive the base of q1. when q1 is driven into saturation, the voltage on the enable lead falls below its lower threshold. the regulator's output is enabled. when the drive current is removed, the voltage on the enable lead rises, the output is switched off and the ic moves into sleep mode where it draws 50 m a (max). by coupling these two controls with the enable lead, the system has added flexibility. once the system is running, the state of the switch is irrelevant as long as the i/o port continues to drive q1. the microprocessor can turn off its own power by withdrawing drive current, once the switch is open. this software control at the i/o port allows the microprocessor to finish key housekeeping functions before power is removed. the logic options are summarized in table 1. table 1. logic control of cs8311 output microprocessor i/o drive switch enable output on closed low on open low on off closed low on open high off the i/o port of the microprocessor typically provides 50 m a to q1. in automotive applications the switch is connected to the ignition switch. stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. v in figure 6. test and application circuit showing output compensation c in * 0.1 m f enable v out r rst c out ** 10 m f reset cs8311 *c in required if regulator is located far from the power supply filter . *c out required for stability. capacitor must operate at minimum temperature expected. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c out shown in figure 6 should work for most applications, however it is not necessarily the optimized solution.
cs8311 http://onsemi.com 6 to determine an acceptable value for c out for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next lar ger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 7) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 7. single output regulator with key performance parameters labeled smart regulator ? control features i out i in i q v in v out heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja . r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it too is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8311 http://onsemi.com 7 package dimensions so8 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m package thermal data parameter so8 unit r q jc typical 45 c/w r q ja typical 165 c/w
cs8311 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 13036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs8311/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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